1. Field of the Invention
The present invention relates to a photoelectric conversion device used in a digital camera, a digital video camera, an endoscope, and the like.
Priority is claimed on Japanese Patent Application. No. 2009-221774, filed Sep. 28, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
Conventionally, a solid-state image-pickup device is used as a photoelectric conversion device used in a digital camera, a digital video camera, an endoscope, and the like. Digital cameras, digital video cameras, endoscopes, and the like including the solid-state image-pickup device are increasingly being made smaller and with reduced power consumption. Therefore, there is a need to make the solid-state image-pickup device smaller and with reduced power consumption.
To response to this need, Japanese Unexamined Patent Application, First Publication, No. 2006-287879 discloses a solid-state image-pickup device that internally incorporates an A/D converter configured as a digital circuit.
FIG. 9 is a block diagram illustrating a schematic configuration of a solid-state image-pickup device in accordance with the related art. The solid-state image-pickup device includes a plurality of array blocks (subarrays) arranged in two dimensions. As an example, in the solid-state image-pickup device of FIG. 9, the array blocks (subarrays) B1, B2, . . . , B20 are arranged in four rows and five columns. Each array block (subarray) includes a two-dimensionally arranged pixel block 90 in which a photoelectric conversion element outputs a pixel signal in accordance with an incident light amount, and an A/D converter 91 that converts the pixel signal output from the pixel of the pixel block 90 from analog to digital.
FIG. 10 is a block diagram illustrating an example of a circuit configuration of an A/D converter 91 included in each of the array blocks (subarrays) of FIG. 9. The A/D converter 91 includes a delay circuit 901 and an encoder 902. The delay circuit 901 includes a plurality of delay units, each of which includes various types of gate circuits, and the delay units are connected in a ring shape. An input signal (input voltage) that will be the object of an analog-digital conversion is input to each delay unit in the delay circuit 901 as a drive voltage for the delay units. Also, a reference voltage is supplied to each delay unit in the delay circuit 901.
In the A/D converter 91 of FIG. 10, if, for example, the reference voltage of the delay circuit 901 is GND, and a high-level signal is input as the input pulse signal φPL, then the input pulse signal φPL will have a delay time that corresponds to the voltage difference between the input signal and the reference voltage (GND) as it passes sequentially through the delay units and circulates around the delay circuit 901. If the input pulse signal φPL is set to the low level, then it will stop circulating around the delay circuit 901.
When the input pulse signal φPL is circulating around the delay circuit 901, the number of stages of the delay units that the input pulse signal φPL passes through within a predetermined period of time is determined based on the delay time of the delay units, i.e. the voltage difference between the input signal and the reference voltage (GND). The encoder 902 detects the passed number of stages of delay units (and the number of circulations).
The encoder 902 includes a counter circuit 9021, a latch and encoder circuit 9022, and an adder 9023. The counter circuit 9021 counts the number of circulations of the input pulse signal φPL around the delay circuit 901. The latch and encoder circuit 9022 detects the number of stages of the input pulse signal φPL travelling around the delay circuit 901. The counter circuit 9021 outputs, for example, a bits of upper bit data. The latch and encoder circuit 9022 outputs, for example, b bits of lower bit data. The adder 9023 outputs a+b bits of digital data. The output value of the adder 9023 becomes a digital value after analog-digital conversion in accordance with the voltage of the input signal. In the solid-state image-pickup device of FIG. 9, the pixel signal output from the pixel block 90 is used as the input signal of the A/D converter 91, whereby a digital value in accordance with the incident light amount is output.
When an A/D converter is mounted in a solid-state image-pickup device, an A/D converter is sometimes provided for each column of the pixel blocks that arrange photoelectric conversion elements in a two-dimensional array. When an A/D converter is provided for each column of pixel blocks in this manner, each one must be arranged longitudinally.
When the A/D converter is arranged longitudinally, the distance between the delay units contained in the delay circuit inside the A/D converter and the latch circuit contained in the latch and encoder circuit will vary in each delay unit stage. FIG. 11 is a block diagram schematically illustrating an example of a layout of constituent components in an A/D converter included in a solid-state image-pickup device in accordance with the related art. Let us consider a case where the delay units and the latch units in the latch circuit are arranged as illustrated in FIG. 11. In FIG. 11, distance a is the distance between the delay units, distance b is the distance between the latch units, and distance c is the distance between the last-stage delay unit Dn and the first-stage latch unit L1. The length of the signal wire interconnection between the delay units and the latch units differs in each stage.
More specifically, the interconnection length d1 of the first-stage delay unit D1 is 3a+c. The interconnection length d2 of the second-stage delay unit D2 is 2a+b+c. The interconnection length d3 of the third-stage delay unit D3 is a+2b+c. The interconnection length do of the nth-stage delay unit Dn is 3b+c. In FIG. 11, the interconnection lengths in the left and right direction of each stage are equal.